僩僢僾乥婎杮忣曬乥僩僺僢僋乥僗僞僢僼乥尋媶撪梕乥尋媶嬈愌乥尋媶愝旛乥妶摦楌巎乥島媊乥尋媶幒乥
変乆偺尋媶幒偱偼丄憱嵏宆僾儘乕僽尠旝嬀乮Scanning Probe Microscope: SPM乯傗揹巕慄業岝乮Electron-Beam Lithography: EBL乯傪拞怱偵丄僫僲儊乕僩儖媺偺挻旝嵶壛岺媄弍傪奐敪丒嬱巊偟側偑傜丄僫僲僥僋僲儘僕乕傗僫僲僄儗僋僩儘僯僋僗偵娭偡傞尋媶妶摦傪揥奐偟偰偄傑偡丅
嬶懱揑偵偼丄尨巕傪惂屼偡傞僫僲僥僋僲儘僕乕傪梡偄偰丄尨巕傗揹巕傪1屄偢偮憖嶌偡傞偙偲偑壜擻側僫僲僄儗僋僩儘僯僋僗僔僗僥儉偺尋媶傗丄婡夿妛廗傗恖岺抦擻側偳偺抦擻忣曬張棟媄弍偺巟墖偵傛傞検巕宯乮扨揹巕懷揹峔憿丄僩儞僱儖愙崌丄尨巕愙崌乯偱偺検巕忬懺偺惂屼偵娭偡傞尋媶傪峴偭偰偄傑偡丅
偙傟傜偺媄弍傪傕偲偵丄嵟嬤偱偼丄僫僲僊儍僢僾傪梡偄偰擼偺僔僫僾僗傪柾曧偟偨僯儏乕儘儌儖僼傿僢僋僨僶僀僗偺奐敪傗丄検巕寁嶼婡偵偍偗傞検巕丒屆揟僴僀僽儕僢僪傾儖僑儕僘儉傪梡偄偨慻傒崌傢偣嵟揔壔庤朄偵傛傞検巕幚尡宯偱偺幚尡僷儔儊乕僞扵嶕偲尨巕愙崌偺嶌惢丄検巕寁嶼婡乮検巕傾僯乕儕儞僌儅僔儞乯傪柾媅偟偨FPGA幚憰宆僀僕儞僌寁嶼婡偺幚尰偲墳梡偵偮偄偰専摙偟偰偄傑偡丅
埲壓偵丄戙昞揑側尋媶撪梕偺僉乕儚乕僪偲娙扨側夝愢傪帵偟傑偡丅傑偨丄幚嵺偺尋媶敪昞偵娭偡傞僞僀僩儖徻嵶偼丄尋媶嬈愌偺崙撪夛媍傗丄僩僺僢僋側偳傪偛棗偔偩偝偄丅
丂 
恖娫偺恎懱傗丄悽奅丒帺慠丒塅拡側偳丄偡傋偰偼検巕偱偱偒偰偄傑偡丅検巕偲偼暔幙傗僄僱儖僊乕偺嵟彫扨埵偱偁傝丄尨巕偼検巕偐傜峔惉偝傟丄揹巕傕傑偨検巕偱偡丅尰嵼偺僫僲僥僋僲儘僕乕偲屇偽傟傞媄弍偼尨巕傪1屄扨埵偱惂屼偟丄偝傜偵丄僫僲僄儗僋僩儘僯僋僗偱偼揹巕傪1屄偢偮憖嶌偟偰偄傑偡丅偟偐偟丄尨巕傗揹巕偺惂屼偼偲偰傕擄偟偔丄偦偺棟夝偵偼検巕椡妛偲屇偽傟傞怴偟偄暔棟妛偑昁梫偱偡丅偙傟傜偺尋媶偼丄検巕寁嶼婡傪尰幚偺傕偺偲偟偮偮偁傝傑偡丅
変乆偺尋媶幒偱偼丄尨巕傗揹巕傪1屄偢偮憖嶌偡傞媶嬌揑側尋媶傪峴偭偰偄傑偡丅偦傟偵偼丄検巕椡妛偺抦幆傗幚尡偺媄擻丒宱尡側偳丄朿戝側抦尒傗媄検傪恎偵晅偗傞昁梫偑偁傝傑偡丅堦曽丄嬤擭丄恖岺抦擻偺惈擻傕戝偒偔岦忋偟偰偒傑偟偨丅偦偙偱変乆偼丄検巕偺悽奅偺擄偟偄尋媶傪恖娫偑峴偆偺偱偼側偔丄揔愗偵愝寁偝傟偨恖岺抦擻(儅僔儞)偵幚峴偝偣傞偙偲傪峫偊偰偄傑偡丅
恖岺抦擻偵巟墖偝傟偨検巕忬懺偺惂屼媄弍偑検巕僨僶僀僗傪帺棩揑偵嶌惢偟丄検巕寁嶼婡偺傛偆側嫮椡側僐儞僺儏乕僞傪惗傒弌偡丅偦傟偑傛傝崅摍側恖岺抦擻傪昞尰偟丄傛傝崅搙側検巕寁嶼婡傪惗傒弌偡丅彨棃丄恖娫偱偼側偔儅僔儞偑尋媶妶摦傪峴偆偐傕偟傟傑偣傫偹丅
CHIP GALLERY (SEVERAL TYPES/KINDS OF
CHIPS FABRICATED IN THE LAB)
KEYWORDS/RESEARCH TOPICS
Nanofabrication: Scanning Probe Microscopy (SPM),
Atomic Force Microscopy (AFM), SPM Local Oxidation Nanolithography, SPM
Scratching Nanolithography, Electron-Beam Lithography
Nanodevices: Single-Electron Transistor (SET),
Ultra-Small Tunnel Junction, Quantum Point Contact (QPC), Ferromagnetic
Nanostructure, Atomic Junction, Artificial Flexible Graphite Thin Film, Strain
Sensor Based on Thin Graphite
Interesting Physical Properties: Single-Electron Charging
Effects, Electromigration (Voltage-Controlled, Field-Emission-Induced),
Magnetoresistance (MR), Anisotropic Magnetoresistance (AMR), Tunnel
Magnetoresistance (TMR), Domain Wall Magnetoresistance (DWMR), Spin
Injection/Current Induced Magnetization Reversal, Human Physiological Signal,
Human Motion Detection, Vital Signs Sensing, Ising Spin Model, New Computing
Architecture, Combinatorial Optimization Problem, Simulated Annealing, Quantum
Annealing, Ising Computing
OUR GROUP'S RESEARCH
focuses on
fabrication of nanodevices and measurement of their electronic and magnetic
properties at low to room temperatures and includes new nanofabrication
techniques, magnetoresistance properties in ferromagnetic nanodevices and
transport properties of electrons through Si and metallic/ferromagnetic
nanostructures such as quantum dots, atomic junctions and nanoconstrictions.
Furthermore, new computing architectures using Ising spin model implemented on
FPGA are also investigated. Monitoring human physiological signals using
artificial flexible graphite thin films are recent research topics in our
group.
SHIRAKASHI
GROUP丂-Nanoelectronics, Nanofabrication and
Nanolithography-
BRIEF DESCRIPTION OF OUR
RESEARCH TOPICS (PARTIALLY)
PhD DISSERTATION
February, 2019, M. Ito:
STUDY ON
INTEGRATION OF ROOM-TEMPERATURE OPERATIONAL SINGLE-ELECTRON TRANSISTORS BY
ELECTROMIGRATION IN SERIES-CONNECTED NANOGAPS
February, 2018, M. Yagi:
STUDY ON IN
SITU MEASUREMENTS OF ELECTROMIGRATED METALLIC NANO新万博体育_万博体育官网-【官方授权牌照】S USING ATOMIC FORCE
MICROSCOPY
August, 2017, R. Suda:
STUDY ON
REDUCTIVE DEPOSITION OF THIN FILMS BASED ON BALLISTIC ELECTRON INCIDENCE
February, 2011, S. Nishimura:
STUDY ON
ADVANCED LITHOGRAPHY TECHNIQUES USING SCANNING PROBE MICROSCOPY FOR FABRICATION
OF NANOSCALE Si DEVICES
February, 2010, Y. Tomoda:
STUDY ON
PLANAR-TYPE FERROMAGNETIC NANOSCALE DEVICES FABRICATED BY NOVEL NANOFABRICATION
TECHNIQUES
POSTER GALLERY
[28] 僫僠儏儔儖僐儞僺儏乕僥傿儞僌傪梡偄偨怴宆寁嶼婡偺奐敪
[27] 掅僐僗僩側僶僀僞儖僒僀儞僙儞僔儞僌媄弍
[26] Field-Emission-Induced
Electromigration for Integration and Control of Nanogaps
[25] Fabrication
of Nanogaps Using Field-Emission-Induced Electromigration with Alternating
Current Bias
[22] Investigation
of Electromigration in Micrometer-Scale Metal Wires by In-Situ Optical
Microscopy
[20] 揹奅曻幩揹棳桿婲宆EM偵傛傞扨揹巕僩儔儞僕僗僞偺廤愊壔偺専摙
[19] 揹奅曻幩揹棳桿婲宆EM偵傛傝嶌惢偟偨扨揹巕僩儔儞僕僗僞偺摿惈惂屼
[18] 僷僢僔儀乕僔儑儞張棟傪巤偟偨僫僲僊儍僢僾揹嬌偵偍偗傞揹奅曻幩揹棳桿婲宆EM偵傛傞摿惈惂屼偺専摙
[17] 揹奅曻幩揹棳桿婲宆EM偵偍偗傞怴偨側捠揹庤朄偺専摙
[16] CCD嬤愒奜僀儊乕僕儞僌偵傛傞嬥懏嵶慄偺壏搙應掕偺専摙
[15] 岝妛尠旝嬀偦偺応娤嶡偵傛傞嬥懏嵶慄僠儍僱儖偱偺僄儗僋僩儘儅僀僌儗乕僔儑儞偺専摙
[14] 暘妱宆揹埑僼傿乕僪僶僢僋僄儗僋僩儘儅僀僌儗乕僔儑儞偵傛傞Ni僫僲僠儍僱儖偺帴婥掞峈摿惈惂屼
[13] 暘妱宆揹埑僼傿乕僪僶僢僋EM偵傛傞嬥懏僫僲僠儍僱儖偺掞峈惂屼惈偺岦忋偵娭偡傞尋媶
[12] 暘妱宆揹埑僼傿乕僪僶僢僋EM偵傛傞儅僀僌儗乕僔儑儞夁掱偺専摙
[10] 揹奅曻幩揹棳桿婲宆EM偵傛傝嶌惢偟偨嫮帴惈僩儞僱儖愙崌偵偍偗傞帴婥掞峈摿惈
[9] Magnetoresistance
Properties of Planar-Type Ferromagnetic Tunnel Junctions with Vacuum Barriers
Fabricated by Field-Emission-Induced Electromigration (Selected for the Best Poster Award of ChinaNANO2009)
[7] Control
of Tunnel Resistance of Si Nanogaps Using Field-Emission-Induced
Electromigration
[6] Improvement
of SPM Local Oxidation Nanolithography on Size Controllability of Si Oxide
Wires
[5] 10
Micrometer-Scale SPM Local Oxidation Lithography (Selected for the Poster Award of TBN2008)
[4] Nanoscale
Patterning of NiFe Surface by SPM Scratch Nanolithography
[3] Control
of Channel Resistance on Metal Nanowires by Electromigration Patterning Method
[2] Magnetoresistance
Properties of Planar-Type Ferromagnetic Nanostructures
[1] Multiscale
SPM Lithography
憱嵏宆僾儘乕僽尠旝嬀乮SPM乯傪梡偄偨僫僲僗働乕儖儕僜僌儔僼傿乕
Nanolithography Using
Scanning Probe Microscopy (SPM)
|
SPM扵恓捈壓偵桿婲偝傟偨嬊強斀墳応傪惂屼偡傞偙偲偱丄悢僫僲儊乕僩儖乣悢儅僀僋儘儊乕僩儖媺偺峔憿懱傪嶌惢偡傞偙偲偑壜擻側儕僜僌儔僼傿乕媄弍偺奐敪傪峴偭偰偄傑偡丅 摿偵丄SPM嬊強巁壔朄偱偼丄摼傜傟偨Si巁壔暔嵶慄偺暆偑10nm埲壓乣2.5兪m偵傢偨傞惂屼惈偺妋棫偵惉岟偟偰偄傑偡丅 傑偨丄SPM僗僋儔僢僠朄偱偼丄暆偑20nm埲壓偺僌儖乕僽傗30nm僺僢僠偺儔僀儞&僗儁乕僗峔憿偺嶌惢偵惉岟偟偰偄傑偡丅 |
|
Scanning probe microscopy (SPM)-based lithography at the micro- and
nano-scales is presented. Our method in SPM local oxidation involves two SPM
tips, one having a robust blunt tip, a 乬micrometer tip乭,
and the other having a sharp tip, a 乬nanometer tip乭. In tapping mode SPM local oxidation, Si oxide wires with sub-10 nm
resolution were produced by precisely tuning the dynamic properties of the
nanometer tip. In order to perform large-scale oxidation, SPM tip with a
contact area of µm2, which is about 104 times larger than
that of the conventional nanometer tip, was prepared. Furthermore, we explore the
possibility of performing the sub-20 nm lithography of Si surfaces using SPM
scratching with a diamond-coated tip. SPM-based lithography plays an important
role for bridging the gap between micro- and nano-scales.
僾儗僫乕宆嫮帴惈僫僲僗働乕儖僩儞僱儖愙崌
Planar-Type Ferromagnetic
Tunnel Junctions (Planar-MTJs)
|
嫮帴惈懱偱嶌惢偝傟偨嬌旝彫側僩儞僱儖愙崌偱偼丄扨揹巕懷揹岠壥偲僗僺儞埶懚僩儞僱儖岠壥偺憡屳嶌梡偵傛傝丄揹壸偲僗僺儞偑摿堎側怳傞晳偄傪帵偟傑偡丅 変乆偑奐敪偟偰偄傞儐僯乕僋側挻旝嵶壛岺媄弍偵傛傝丄僾儗僫乕宆峔憿偺嫮帴惈僩儞僱儖愙崌傪嶌惢偟丄揹婥揑丒帴婥揑摿惈傪専摙偟偰偄傑偡丅 SPM嬊強巁壔朄偱嶌惢偟偨Ni宯僩儞僱儖愙崌偱偼丄17K偲偄偆掅壏偱偼偁傝傑偡偑丄100%傪墇偊傞帴婥掞峈岠壥傪娤應偟偰偄傑偡丅 |
|
Nanometer-scale oxide wires were fabricated by local oxidation
nanolithography using scanning probe microscope (SPM). This technique was
applied to the fabrication of planar-type Ni/Ni oxide/Ni ferromagnetic tunnel
junctions. In order to induce magnetic shape anisotropy, asymmetrical channel
structure was patterned by conventional photolithography and wet etching
processes. The magnetoresistance (MR) characteristics were clearly shown in the
planar-type Ni/Ni oxide/Ni ferromagnetic tunnel junctions. MR ratio of above
100 % was obtained at 17 K. This result suggests that the local oxidation
nanolithography using SPM is useful for the application to planar-type
ferromagnetic tunnel junctions.
嫮帴惈扨揹巕僩儔儞僕僗僞
Ferromagnetic
Single-Electron Transistors (FMSETs)
|
嫮帴惈僫僲僗働乕儖僩儞僱儖愙崌偐傜側傞嫮帴惈扨揹巕僩儔儞僕僗僞慺巕傗僔僗僥儉偺採埬丒専摙傪峴偭偰偄傑偡丅 梕検寢崌宆丄掞峈寢崌宆丄RC寢崌宆偲偄偆3庬椶偺婎杮慺巕峔憿偺採埬偲悢抣寁嶼偵傛傞揹婥揑丒帴婥揑摿惈偺梊應傪峴偄丄幚嵺偺慺巕峔憿偺嶌惢偲慺巕摿惈偺専摙傪峴偭偰偄傑偡丅 嫮帴惈扨揹巕僩儔儞僕僗僞偱偼丄揹巕偺2帺桼搙乮僗僺儞丒揹壸乯傪惂屼偱偒傞壜擻惈偑偁傝丄儐僯乕僋側帴婥掞峈摿惈偺敪尰丒惂屼傪捠偟偰丄崅惈擻側儊儌儕乕僔僗僥儉偺幚尰偑婜懸偝傟傑偡丅 |
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We study quantitatively the operation of ferromagnetic single-electron
transistors coupled to the controlling gate potential by the gate resistance
and gate capacitance in series. In this type of the device, several metastable
charge states are possible within the Coulomb blockade range. The enhancement
and hysteresis of tunnel magnetoresistance on the drain and gate voltages are
predicted. Inelastic macroscopic quantum tunneling of charge and the existence
of several charge states play an important role for the unique behavior of the
tunnel magnetoresistance. This implies that RC-coupled ferromagnetic
single-electron transistors have a new functionality as novel magnetoresistive
nanostructure devices.
Si宯扨揹巕僩儔儞僕僗僞
Si-Based Single-Electron
Transistors (Si-SETs)
|
Si傪梡偄偨扨揹巕僩儔儞僕僗僞媄弍偼丄尰忬偺敿摫懱廤愊夞楬媄弍偲偺惍崌惈偲偄偆娤揰偐傜旕忢偵廳梫偱偡丅 SOI (Silicon on Insulator) 婎斅傪梡偄丄幒壏摦嶌偑壜擻側Si宯扨揹巕僩儔儞僕僗僞傪廬棃偺敿摫懱僾儘僙僗傪捠偟偰斾妑揑娙曋偵嶌惢偡傞偙偲偑偱偒傞媄弍傪奐敪偡傞偲偲傕偵丄摼傜傟偨慺巕摿惈偺幒壏偱偺昡壙偐傜丄摉奩媄弍偺桳梡惈傪専摙偟偰偄傑偡丅 |
|
Single-electron charging effects are studied in Si-based single-electron
transistors (Si-SETs) at room temperature. The SETs were first fabricated by a
conventional Electron-Beam (EB) lithography method. Then the miniaturization of
tunnel junctions was further performed by scanning probe microscopy (SPM)-based
nanolithography techniques such as SPM local oxidation and SPM scratching.
Ultra-low capacitance tunnel junctions were easily obtained by utilizing both
kinds of nanofabrication processes, which realizes room temperature operation
of Si-SETs.
僄儗僋僩儘儅僀僌儗乕僔儑儞傪梡偄偨幒壏摦嶌扨揹巕僨僶僀僗偺娙曋側嶌惢媄弍
Controlled Electromigration
for Nanodevice Fabrication/Integration (Activation)
|
扨揹巕僨僶僀僗偱偼丄偦偺嬌旝嵶側峔憿傪擛壗偵惂屼偝傟偨宍偱慺巕峔憿偲偟偰嬶尰壔偡傞偐丄偑栤傢傟傑偡丅幒壏摦嶌傪栚巜偡応崌丄10nm埲壓媺偺峔憿懱傪崅偄惂屼惈偺傕偲偱妋幚偵嶌惢偡傞媄弍偑昁梫偲側傝傑偡丅 僄儗僋僩儘儅僀僌儗乕僔儑儞傪梡偄傞偙偲偱丄幒壏摦嶌偑壜擻側扨揹巕僨僶僀僗傪娙曋偵嶌惢偡傞偙偲偑偱偒傞怴偟偄媄弍乮傾僋僥傿儀乕僔儑儞朄乯傪憤崌揑偵奐敪偡傞偲偲傕偵丄摼傜傟偨慺巕摿惈偺昡壙偐傜丄摉奩媄弍偺桳梡惈傪専摙偟偰偄傑偡丅 |
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We report a simple and easy technique for the fabrication of nanogaps
with the separations of less than 10 nm. This technique is based on
electromigration induced by field emission current. Here, we investigated the
dependence of tunnel resistance on the shape of nanogap electrodes and initial
gap separation. The initial nanogap electrodes having asymmetrical shape with
the separation of 30-60 nm were fabricated by electron-beam lithography and
lift-off process. In the nanogaps with asymmetrical shape, the tunnel
resistance was controlled by the magnitude of the preset current during
field-emission-induced electromigration and decreased from the order of 100 TΩ to 100 kΩ with increasing the preset current from 1 nA to 150 µA. This
tendency was quite similar to that of nanogaps with symmetrical shape.
Furthermore, the tunnel resistance after the electromigration was less
dependent on the initial gap separation and was completely determined by the
preset current. This result suggests that it is possible to perform the control
of tunnel resistance of nanogaps by field-emission-induced electromigration.
僄儗僋僩儘儅僀僌儗乕僔儑儞傪梡偄偨Au尨巕愙崌偺嶌惢偲検巕壔僐儞僟僋僞儞僗偺惂屼
Ultrafast
Feedback-Controlled Electromigration Using a Field-Programmable Gate Array
(FPGA-Based FCE)
|
尨巕僗働乕儖偺僫僲僊儍僢僾揹嬌傪嶌惢偡傞庤朄偲偟偰丄僄儗僋僩儘儅僀僌儗乕僔儑儞偺敪尰嫮搙傪報壛揹埑偺僼傿乕僪僶僢僋偵傛傝挷惍偡傞僼傿乕僪僶僢僋惂屼宆僄儗僋僩儘儅僀僌儗乕僔儑儞乮FCE乯朄偑抦傜傟偰偄傑偡丅 杮尋媶偱偼丄Field-Programmable Gate Array (FPGA)
傪梡偄偨挻崅懍FCE朄偵傛傝丄儅僀僋儘昩僆乕僟偱偺Au尨巕偺堏摦惂屼庤朄傪妋棫偟丄尨巕愙崌偺嶌惢傗検巕壔揱摫偺帺棩揑側惂屼傪専摙偟偰偄傑偡丅 |
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Feedback-controlled electromigration (FCE) has been a useful technique
for creating nanoscale gaps between metal electrodes. In general, it is
considered that the fabrication of nanogaps by the conventional FCE method
using a microprocessor-based control system is a very time consuming and slow
process. Here, the authors propose an ultrafast FCE method using a
field-programmable gate array (FPGA) to immediately and precisely control the
channel resistance of metal nanowires at room temperature. Using the ultrafast
FCE method based on an FPGA, the channel resistance of Au micrometer wires was
precisely controlled from 100 to 10,000 Ω within 1 sec at room temperature, and
without catastrophic breaks of the Au micrometer wires. Furthermore, the total
process time of the FPGA-based ultrafast FCE procedure was considerably
shortened without degradation of the controllability of the channel resistance
of the Au micrometer wires, and is 1,000 to 10,000 times shorter than that of
conventional FCE. These results imply that ultrafast FCE using an FPGA can
precisely and stably control the channel resistance of Au micrometer wires with
a shortened process time.
恖憿崟墧僔乕僩偵傛傞榗曄埵僙儞僒傪梡偄偨惗懱忣曬儌僯僞儕儞僌僨僶僀僗偺奐敪
Monitoring Human Physiological Signals Using Artificial Flexible
Graphite Thin Films
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杮尋媶偱偼丄崅偄廮擃惈傪桳偟壛岺偑梕堈側恖憿崟墧僔乕僩偵拝栚偟丄掅僐僗僩偐偮崅姶搙側榗僙儞僒偺奐敪偲惗懱忣曬儌僯僞儕儞僌僨僶僀僗偲偟偰偺墳梡傪専摙偟偰偄傑偡丅 娭愡摦嶌丄懌掙壸廳暘晍丄柆攈丄屇婥丄昞忣偺曄壔側偳丄恖懱偺妶摦偵敽偆朿戝側僶僀僞儖僒僀儞忣曬傪僐儞僺儏乕僞偱妛廗偝偣丄"Real-Time Health Management System"傪採埬丒専摙偟偰偄傑偡丅 |
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In this study, the electrical properties of thin graphite wires were
investigated for strain sensors. The thin graphite wires were simply and easily
fabricated from pyrolytic graphite sheet, which can be formed by firing a
polymer film (such as a polyimide film) at high temperatures. The resistance of
the thin graphite wires increased under increasing tensile bending strains, and
decreased under increasing compressive bending strains. Notably, the
sensitivity of the sensors increased when the thickness of the thin graphite
wires was reduced. This property was investigated via modeling of the
strain-induced changes in the overlap area and conduction pathways of the graphite
flakes. Multiple-cycle tests were carried out to evaluate the long-term
stability of the thin graphite wires; specifically, the electrical response was
monitored under repeated cycling, for approximately 1,000 cycles. The thin
graphite wires were assembled on ultra-thin gloves to fabricate data gloves
that could detect finger motions. The results of this study indicate that the
thin graphite wires that were simply and easily fabricated from pyrolytic
graphite sheet have great potential for a wide range of applications, including
human motion detectors.
暔棟尰徾傪柾媅偟偨怴偟偄奣擮偺僐儞僺儏乕僥傿儞僌媄弍偺奐敪
A New Computing
Architecture Using Ising Spin Model Implemented on FPGA for Solving
Combinatorial Optimization Problems
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廬棃偺僲僀儅儞宆僐儞僺儏乕僞偱偼乽慻傒崌傢偣嵟揔壔栤戣乿傪岠棪揑偵夝偔偙偲偼擄偟偄偙偲偑抦傜傟偰偄傑偡丅偙偺栤戣傪尰幚偺僐僗僩丒帪娫僗働乕儖偱夝偔偙偲偑偱偒傟偽丄恖岺抦擻偺奐敪傗戝婯柾偱暋嶨壔偟偨幮夛僔僗僥儉偺嵟揔壔傪払惉偡傞偙偲偑偱偒傑偡丅 嬤擭丄慻傒崌傢偣嵟揔壔栤戣傪夝偔偨傔偵丄嫮帴惈懱偱偺僗僺儞偺怳傞晳偄傪昞尰偡傞乽僀僕儞僌僗僺儞儌僨儖乿偑拲栚傪廤傔偰偄傑偡丅杮尋媶偱偼丄僀僕儞僌僗僺儞儌僨儖傪FPGA偵幚憰偟丄帺慠奅偺僄僱儖僊乕廂懇摦嶌傪柾媅偟偨怴偟偄乮旕僲僀儅儞宆乯僐儞僺儏乕僥傿儞僌媄弍偺僴乕僪僂僃傾壔乮僀僕儞僌僗僺儞寁嶼婡乯偲慻傒崌傢偣嵟揔壔栤戣傊偺揔梡傪専摙偟偰偄傑偡丅 |
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It is well known that Ising spin model represents the physical properties
of ferromagnetic materials in terms of statistical mechanics. In this model,
the spin states are varied in order to minimize the system energy
automatically, by the interaction between connected adjacent spins. The system
Hamiltonian H, the total energy of the system, is described using the following
formula: H = ‒ 嚁Jij冃i冃j ‒ 嚁hi冃i, where 冃i and 冃j represent spin states (+1 or ‒1) at
neighboring site i and j, Jij is the interaction coefficient between spins, and
hi is the external magnetic field coefficient. Recently, the new computing
architecture called Ising computing has been proposed using superconductors and
CMOS circuits, in order to simulate the Ising spin model, in which this method
maps the combinatorial optimization problems to the ground state search of the
model. Here, a new computing architecture using Ising spin model was
implemented using logic gates, and the Ising computing based on logic gates was
investigated to solve combinatorial optimization problems.
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